سال انتشار: ۱۳۸۸

محل انتشار: سومین کنفرانس نانوساختارها

تعداد صفحات: ۴

نویسنده(ها):

Keivan Navi – Department of Electrical & Computer Engineering Shahid Beheshti University, Tehran
Omid Daei – Nano-Technology & Quantum Computing Lab of Shahid Beheshti University, GC and IAU, Tehran, Iran
Peiman Keshavarzian – Nano-Technology & Quantum Computing Lab of Shahid Beheshti University, GC and IAU, Tehran, Iran,
Mohammad Reza Saatchi – Nano-Technology & Quantum Computing Lab of Shahid Beheshti University, GC and IAU, Tehran, Iran,

چکیده:

An ultra high speed two transistor Full Adder is presented in this article. The main purpose of designing this full adder is achieving a very high speed Full Adder. In CMOS conventional adder cells up to 28 transistors are used in order to implement it. In this design based on Carbon Nanotube (CNT) and Majority function we have achieved a significant improvement in terms of speed. Besides, in order to reduce the power dissipation we propose another 4 transistors full adder which is slightly slower than the 2 transistors but consumes much less power. Simulation results demonstrate improvement in terms of power-delay product and significant improvement in terms of speed in comparison to the conventional and current implementation of the 1-bit Full Adder cells.